The present disclosure herein relates to semiconductor devices, and more particularly, to charge trapping nonvolatile memory devices.
A nonvolatile memory device based on charge trapping mechanism typically includes a charge storage layer between a control gate and a channel and is largely classified into a floating gate type and a charge trapping type according to how charge is stored therein. A floating gate type nonvolatile memory device generally uses an electrically-isolated conductive pattern (i.e., a floating gate) for charge storage and a charge trapping nonvolatile memory device general uses an insulation layer (e.g., a silicon nitride layer) having a high trap site density for charge storage. Until now, the floating gate type nonvolatile memory generally has better reliability than the charge trapping nonvolatile memory device. As a result, most nonvolatile memory devices are floating gate type devices due to their reliability and other possible technical advantages.
As line pattern widths are reduced in order to increase memory capacity, various difficulties can arise with, for example, providing a sufficient coupling ratio. Consequently, it is expected that future nonvolatile memory may increasingly use charge trapping type devices or 3-D charge trapping type devices. For example, according to the 2009 edition of the International Technology Roadmap for Semiconductors (ITRS), it has been noted that materials that may be used for a gate interlayer insulation layer or an interpoly dielectric have not yet been identified that can provide a sufficient coupling ratio to meet projected trends with line pattern widths, etc. Accordingly, ITRS 2009 expects that the floating gate devices and charge trapping devices will coexist from 2012 to 2013 and that 3-D charge trapping type flash memories will be shipped to the markets in 2014. However, in order for 3-D charge trapping type flash memory to reach a mass production state, techniques that satisfy technical requirements related to data retention characteristics and operating speeds are required.